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NUP4212UPMU Quad Transient Voltage Suppressor Array
ESD Protection Diodes with Ultra-Low (0.7 pF) Capacitance
The four-line voltage transient suppressor array is designed to protect voltage-sensitive components that require ultra-low capacitance from ESD and transient voltage events. This device features a common anode design which can protect up to four independent high speed data lines and 1 or 2 separate 15 V TVS lines in a single six-lead UDFN low profile package. Excellent clamping capability, low capacitance, low leakage, and fast response time make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, it is suited for use in high frequency designs such as a USB 2.0 high speed. This device can be configured as a dual port USB device.
Features http://onsemi.com
D1 D2 D3 D4 V1 V2
* * * * * * * * * * * *
Low Capacitance Data Lines (0.7 pF Typical) Protects up to Four Data Lines Plus a VCC Pin UDFN Package, 1.6 x 1.6 mm Low Profile of 0.50 mm for Ultra Slim Design V1, V2 Pin = 15 V Protection D1, D2, D3, and D4 Pins = 5.2 V Minimum Protection ESD Rating: IEC61000-4-2: Level 4 - Contact (14 kV) This is a Pb-Free Device USB 2.0 High-Speed Interface Cell Phones MP3 Players SIM Card Protection
MARKING DIAGRAM
6 1 P2 M G UDFN6 1.6 X 1.6 MU SUFFIX CASE 517AP 1 P2 MG G
= Specific Device Code = Date Code = Pb-Free Package
(Note: Microdot may be in either location)
Typical Applications
PIN CONNECTIONS
D1 1 D2 2 D3 3 GND 6 5 4 V2 V1 D4
MAXIMUM RATINGS (TJ = 25C, unless otherwise specified)
Symbol TJ TSTG TL ESD Rating Operating Junction Temperature Range Storage Temperature Range Lead Solder Temperature - Maximum (10 seconds) IEC 61000-4-2 Contact Value -40 to 125 -55 to 150 260 14000 Unit C C C V
ORDERING INFORMATION
Device NUP4212UPMUTAG Package Shipping
UDFN6 3000/Tape & Reel (Pb-Free)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
See Application Note AND8308/D for further description of survivability specs.
(c) Semiconductor Components Industries, LLC, 2009
August, 2009- Rev. 1
1
Publication Order Number: NUP4212UPMU/D
NUP4212UPMU
ELECTRICAL CHARACTERISTICS
(TA = 25C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT IF VF Ppk C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Forward Current Forward Voltage @ IF Peak Power Dissipation Max. Capacitance @ VR = 0 and f = 1.0 MHz IPP VC VBR VRWM IR VF IT V IF I
Uni-Directional TVS
*See Application Note AND8308/D for detailed explanations of datasheet parameters.
ELECTRICAL CHARACTERISTICS (TJ = 25C, unless otherwise specified)
Parameter Reverse Working Voltage (D1, D2, D3, and D4) Reverse Working Voltage (V1 and V2) Breakdown Voltage (D1, D2, D3, and D4) Breakdown Voltage (V1, V2) Reverse Leakage Current (D1, D2, D3, and D4) Reverse Leakage Current (V1, V2) Capacitance (D1, D2, D3, and D4) Clamping Voltage Clamping Voltage (Note 1) (Note 1) IT = 1 mA, (Note 2) IT = 5 mA, (Note 2) @ VRWM1 @ VRWM2 VR = 0 V, f = 1 MHz (Line to GND) @ IPP = 1 A (Note 3) Per IEC61000-4-2 (Note 4) Conditions Symbol VRWM1 VRWM2 VBR VBR2 IR IR CJ VC VC Min - - 5.2 13.5 - - - - Typ - - 5.5 15 - - 0.7 - Max 4.0 12 - 15.8 1.0 1.0 0.9 14.3 Unit V V V V mA mA pF V V
Figures 1 and 2
1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 2. VBR is measured at pulse test current IT. 3. Surge current waveform per Figure 5. 4. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000-4-2
Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000-4-2
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NUP4212UPMU
IEC 61000-4-2 Spec.
Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC61000-4-2 Waveform Ipeak 100% 90%
Level 1 2 3 4
Figure 3. IEC61000-4-2 Spec
ESD Gun
TVS
Oscilloscope
50 W Cable
50 W
Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D - Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger
100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr
systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.
PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms
40 t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
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NUP4212UPMU
PACKAGE DIMENSIONS
UDFN6, 1.6x1.6, 0.5P CASE 517AP-01 ISSUE O
D
2X
A B L1 E DETAIL A
0.10 C
L
2X
0.10 C
DETAIL B
(A3)
A A1
0.05 C
6X
DETAIL B
OPTIONAL CONSTRUCTION
0.05 C SIDE VIEW A1 C
SEATING PLANE
DETAIL A 6X
L
D2
1 3
E2
6X
K e
6
5
6X
b 0.10 C A B 0.05 C
NOTE 3
BOTTOM VIEW
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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EE EE EE EE
EE EE
PIN ONE REFERENCE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D E e D2 E2 K L L1 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 1.60 BSC 1.60 BSC 0.50 BSC 1.10 1.30 0.45 0.65 0.20 --- 0.20 0.40 0.00 0.15
OPTIONAL CONSTRUCTION EXPOSED Cu MOLD CMPD
TOP VIEW
A3
SOLDERMASK DEFINED MOUNTING FOOTPRINT*
1.26
0.52
6X
0.61 1.90
1 0.50 PITCH
6X
0.32
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NUP4212UPMU/D

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